 |
Journal articles
Simplified topology for IC buffer behavioural models
Abstract : This paper addresses the behavioural modelling of digital integrated circuit buffers for performance assessment of high-speed data links. A new modelling technique, with several important advantages is described. All the requirements of black-box identification are met: the approach relies exclusively on the observation of the external port voltages and currents, thus allowing the extraction of models that mimic the operation of real devices without insight on their internal structure. Furthermore, unlike the standard algorithms currently used in EDA tools, the method described in this paper provides a straightforward solution to modelling the input-output behaviour. Good model performance in overclocking conditions is an important advantage. The paper also investigates the possibility of accounting for power-supply voltage variations and provides a simple solution.
https://hal.univ-brest.fr/hal-01490858
Contributor : Noël Tanguy Connect in order to contact the contributor
Submitted on : Thursday, March 16, 2017 - 9:56:28 AM
Last modification on : Monday, March 14, 2022 - 11:08:13 AM
Long-term archiving on: : Saturday, June 17, 2017 - 12:31:58 PM
Contributor : Noël Tanguy Connect in order to contact the contributor
Submitted on : Thursday, March 16, 2017 - 9:56:28 AM
Last modification on : Monday, March 14, 2022 - 11:08:13 AM
Long-term archiving on: : Saturday, June 17, 2017 - 12:31:58 PM
File
Diouf_et_all_IET2017_vfinale.p...
Files produced by the author(s)