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Journal Articles IET Circuits, Devices & Systems Year : 2017

Simplified topology for IC buffer behavioural models


This paper addresses the behavioural modelling of digital integrated circuit buffers for performance assessment of high-speed data links. A new modelling technique, with several important advantages is described. All the requirements of black-box identification are met: the approach relies exclusively on the observation of the external port voltages and currents, thus allowing the extraction of models that mimic the operation of real devices without insight on their internal structure. Furthermore, unlike the standard algorithms currently used in EDA tools, the method described in this paper provides a straightforward solution to modelling the input-output behaviour. Good model performance in overclocking conditions is an important advantage. The paper also investigates the possibility of accounting for power-supply voltage variations and provides a simple solution.
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Dates and versions

hal-01490858 , version 1 (16-03-2017)



Chérif El Valid Diouf, Mihai Telescu, Igor S Stievano, Noël Tanguy, Flavio G Canavero. Simplified topology for IC buffer behavioural models. IET Circuits, Devices & Systems, 2017, 11 (2), pp.183-187. ⟨10.1049/iet-cds.2015.0368⟩. ⟨hal-01490858⟩
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