Simplified topology for IC buffer behavioural models - Université de Bretagne Occidentale Access content directly
Journal Articles IET Circuits, Devices & Systems Year : 2017

Simplified topology for IC buffer behavioural models

Abstract

This paper addresses the behavioural modelling of digital integrated circuit buffers for performance assessment of high-speed data links. A new modelling technique, with several important advantages is described. All the requirements of black-box identification are met: the approach relies exclusively on the observation of the external port voltages and currents, thus allowing the extraction of models that mimic the operation of real devices without insight on their internal structure. Furthermore, unlike the standard algorithms currently used in EDA tools, the method described in this paper provides a straightforward solution to modelling the input-output behaviour. Good model performance in overclocking conditions is an important advantage. The paper also investigates the possibility of accounting for power-supply voltage variations and provides a simple solution.
Fichier principal
Vignette du fichier
Diouf_et_all_IET2017_vfinale.pdf (1.37 Mo) Télécharger le fichier
Origin : Files produced by the author(s)

Dates and versions

hal-01490858 , version 1 (16-03-2017)

Identifiers

Cite

Chérif El Valid Diouf, Mihai Telescu, Igor S Stievano, Noël Tanguy, Flavio G Canavero. Simplified topology for IC buffer behavioural models. IET Circuits, Devices & Systems, 2017, 11 (2), pp.183-187. ⟨10.1049/iet-cds.2015.0368⟩. ⟨hal-01490858⟩
125 View
327 Download

Altmetric

Share

Gmail Facebook X LinkedIn More