Simplified topology for IC buffer behavioural models

Chérif El Valid Diouf 1, 2 Mihai Telescu 2, 3 Igor Stievano 4 Noël Tanguy 2, 3 Flavio Canavero 4
1 Lab-STICC_UBO_MOM_DIM
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance, UBO - Université de Brest
2 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
3 Lab-STICC_UBO_MOM_PIM
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance, UBO - Université de Brest
4 EMC Group
Abstract : This paper addresses the behavioural modelling of digital integrated circuit buffers for performance assessment of high-speed data links. A new modelling technique, with several important advantages is described. All the requirements of black-box identification are met: the approach relies exclusively on the observation of the external port voltages and currents, thus allowing the extraction of models that mimic the operation of real devices without insight on their internal structure. Furthermore, unlike the standard algorithms currently used in EDA tools, the method described in this paper provides a straightforward solution to modelling the input-output behaviour. Good model performance in overclocking conditions is an important advantage. The paper also investigates the possibility of accounting for power-supply voltage variations and provides a simple solution.
Type de document :
Article dans une revue
IET Circuits, Devices & Systems, Institution of Engineering and Technology, 2017, 11 (2), pp.183-187. 〈10.1049/iet-cds.2015.0368〉
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http://hal.univ-brest.fr/hal-01490858
Contributeur : Noël Tanguy <>
Soumis le : jeudi 16 mars 2017 - 09:56:28
Dernière modification le : mardi 16 janvier 2018 - 15:54:26
Document(s) archivé(s) le : samedi 17 juin 2017 - 12:31:58

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Chérif El Valid Diouf, Mihai Telescu, Igor Stievano, Noël Tanguy, Flavio Canavero. Simplified topology for IC buffer behavioural models. IET Circuits, Devices & Systems, Institution of Engineering and Technology, 2017, 11 (2), pp.183-187. 〈10.1049/iet-cds.2015.0368〉. 〈hal-01490858〉

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