Skip to Main content Skip to Navigation
New interface
Conference papers

Laguerre-Gram reduced order modeling applied to VLSI circuit interconnects

Abstract : Reduced order modeling has become a vital tool for decreasing computational cost in time domain simulations. In this paper we present a Laguerre-Gram model-order reduction technique applied to admittance matrices of circuit interconnect lines. We show reduction results for a single line and for a system of two coupled lines but also an iterative solution for obtaining better low order approximations of delayed signals.
Complete list of metadata

Cited literature [9 references]  Display  Hide  Download
Contributor : Noël Tanguy Connect in order to contact the contributor
Submitted on : Thursday, April 1, 2010 - 11:29:15 AM
Last modification on : Wednesday, October 20, 2021 - 2:37:04 PM
Long-term archiving on: : Friday, July 2, 2010 - 8:44:41 PM


Publisher files allowed on an open archive



Mihai Telescu, Pascale Bréhonnet, Noël Tanguy, Pierre Vilbé, Léon-Claude Calvez. Laguerre-Gram reduced order modeling applied to VLSI circuit interconnects. IEEE PRIME (Ph.D. Research in Microelectronics and Electronics), Jul 2005, Lausanne, Switzerland. pp.119 - 122, ⟨10.1109/RME.2005.1542951⟩. ⟨hal-00469005⟩



Record views


Files downloads