Laguerre-Gram reduced order modeling applied to VLSI circuit interconnects
Abstract
Reduced order modeling has become a vital tool for decreasing computational cost in time domain simulations. In this paper we present a Laguerre-Gram model-order reduction technique applied to admittance matrices of circuit interconnect lines. We show reduction results for a single line and for a system of two coupled lines but also an iterative solution for obtaining better low order approximations of delayed signals.
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