A Design Approach to Automatically Synthesize ANSI-C Assertions during High-Level Synthesis of Hardware Accelerators

Mohamed Ben Hammouda; Philippe Coussy; Loic Lagadec

A Design Approach to Automatically Synthesize ANSI-C Assertions during High-Level Synthesis of Hardware Accelerators

Mohamed Ben Hammouda ¹ Philippe Coussy ² Loic Lagadec ³

UBO - Université de Brest, Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance

2 Lab-STICC_UBS_CACS_MOCS

Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance

3 Lab-STICC_ENSTAB_CACS_MOCS ; IDM

STIC - Pôle STIC [Brest], Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance

Abstract : Evolution of Systems-On-Chip (SoC) increases the challenge of verification and post-silicon debug. Nowadays, Assertion Based Verification (ABV) is a widely used methodology. Languages like PSL (Property Specification Language) or SVA (System Verilog Assertions) allows engineers to define properties at Register Transfer Level (RTL). Properties can then be used to generate simulation/hardware assertion checkers for dynamic verification. In this paper, we propose to consider ANSI-C assertions during High-Level Synthesis (HLS) of hardware accelerators (HWacc) to automatically generate on-chip monitors (OCM). The proposed method is portable to any HLS tool and supports both static and dynamic application behaviors. OCM is implemented separately from the HWacc and an original technique is introduced for their synchronization. Two synthesis options are proposed for the OCM design i.e. speed and area. Experimental results show the interest of the proposed approach: while the cost of the OCMs mainly depends on the complexity of input assertions, setting synthesis option is area allows reducing the complexity of the OCM by 2.37x on average compared to the option for speed optimization.

Keywords : High Level Synthesis Assertion Based Verification Hardware Monitoring

Type de document :

Communication dans un congrès

ISCAS 2014 - IEEE International Symposium on Circuits and Systems, May 2014, Melbourne, Australia. pp.XX, 2014

Liste complète des métadonnées

https://hal.univ-brest.fr/hal-00944548
Contributeur : Loic Lagadec <>
Soumis le : lundi 10 février 2014 - 17:03:33
Dernière modification le : jeudi 29 novembre 2018 - 16:51:38

A Design Approach to Automatically Synthesize ANSI-C Assertions during High-Level Synthesis of Hardware Accelerators

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