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A framework for high-level synthesis of heterogeneous MP-SoC

Youenn Corre 1 Jean-Philippe Diguet 2 Dominique Heller 2 Loic Lagadec 3
1 MOCS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
2 Lab-STICC_UBS_CACS_MOCS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
3 MOCS;IDM
STIC - Département STIC [Brest], Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
Abstract : In this paper we propose an ESL synthesis framework which, from the C code of an application and a description of a generic architecture, automatically explores and generates a complete synthesizable version of a H-MPSoC architecture along with the adapted code application. We developed a Design Space Exploration (DSE) algorithm that merges hardware specialization, data-parallelism exploration, processor instantiation and task mapping according to user performance and cost constraints. We also inserted HLS in the DSE loop and get fast exploration of hardware acceleration. A new ESL framework is presented, it combines our contributions with some legacy tools issued from our and another team. We validated our framework with a case study of an MJPEG decoder
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https://hal.univ-brest.fr/hal-00726481
Contributor : Loic Lagadec Connect in order to contact the contributor
Submitted on : Thursday, August 30, 2012 - 12:01:35 PM
Last modification on : Friday, May 7, 2021 - 10:35:20 AM

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Youenn Corre, Jean-Philippe Diguet, Dominique Heller, Loic Lagadec. A framework for high-level synthesis of heterogeneous MP-SoC. GLSVLSI, May 2012, Salt Lake City, United States. pp.283-286, ⟨10.1145/2206781.2206850⟩. ⟨hal-00726481⟩

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