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Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder

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https://hal.univ-brest.fr/hal-00490480
Contributor : Erwan Fabiani Connect in order to contact the contributor
Submitted on : Tuesday, June 8, 2010 - 5:17:54 PM
Last modification on : Monday, October 11, 2021 - 2:23:11 PM

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Samar Yazdani, Thierry Goubier, Bernard Pottier, Catherine Dezan. Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder. ARC 2009, the 5th International Workshop on Applied Reconfigurable Computing, Mar 2009, Germany. pp.287-292, ⟨10.1007/978-3-642-00641-8_30⟩. ⟨hal-00490480⟩

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