Morpheus promotes the transparent use of heterogeneous reconfigurable resources in system on chip. Given the variety of reconfigurable architectures and low level specification languages, it is necessary to use a robust methodology to isolate the application description languages from the possible architectural targets. The WP2 consortium has adopted the idea of a common format for algorithm description that could be used as a crosspoint for sources and targets. This format is a kind of hierarchical Control Data Flow Graph addressed by an application programming interface (API). An input language compiler can then generate processing description to this API producing library or files for the synthesis tools. As for now several tools output CDFG description: Cascade from CriticalBlue, SPEAR from Thales TRT, SpecEDIT from Alcatel Lucent (the CDFG use of SpecEDIT is presented in another paper), AVEL (concurrent processes system description environment) from Lester. The aim of this paper is to present CDFG platform and its integration in the WP2 flow. This goes through defining the CDFG structure (formal description in EXPRESS) and building methodology and its associated tools (rules checker, interchange via STEP files). The transformations performed over the resulting CDFGs, partitioning, mapping, scheduling, and synthesis, are detailed in a complementary paper.