Model-order reduction of VLSI circuit interconnects via a Laguerre representation

Abstract : The VLSI (very large scale integration) industry has the tendency to decrease circuit size, increase speed, assuring ever lower energy consumption and ever higher integration density of analogical components accompanied by digital blocks. With this tendency circuit designers are faced with a new challenge: the analysis and modeling of logical and analogical signals propagating between two circuit points. The search for high speed applications makes the effects of interconnects, usually neglected in the past, an important issue; noise, delay, distortion, reflections and cross talk are just some of these effects. High integration density, miniaturization, high working frequencies are three great factors which prevent interconnects to be considered small independent circuits. Thus, simulation becomes a rather difficult task. Still, wouldn't it be possible to replace complete interconnect equivalent circuits by simpler and more flexible models. Our new model-order reduction technique is mainly based on the use of the Laguerre representation and a simple operator used to generate an approximation base.
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Communication dans un congrès
11th IEEE Workshop on Signal Propagation on Interconnects, May 2005, Garmisch-Partenkirchen, Germany. pp.107 - 110, 2005, 〈10.1109/SPI.2005.1500914〉
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Mihai Telescu, Noël Tanguy, Pascale Bréhonnet, Pierre Vilbé, Léon-Claude Calvez, et al.. Model-order reduction of VLSI circuit interconnects via a Laguerre representation. 11th IEEE Workshop on Signal Propagation on Interconnects, May 2005, Garmisch-Partenkirchen, Germany. pp.107 - 110, 2005, 〈10.1109/SPI.2005.1500914〉. 〈hal-00469111〉

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