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Low Complexity Equivalent Circuit Models for VLSI Interconnects

Abstract : In this paper we present a technique for generating low complexity equivalent circuit models for VLSI circuit interconnects via the Laguerre-Gram model order reduction (MOR) method developed by our team. We discuss model passivity and equivalent circuit implementation and then show the advantages of our method in preserving important signal parameters such as rise time, delay and overshoot.
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Contributor : Noël Tanguy Connect in order to contact the contributor
Submitted on : Thursday, April 1, 2010 - 10:58:06 AM
Last modification on : Wednesday, October 20, 2021 - 2:37:04 PM
Long-term archiving on: : Friday, July 2, 2010 - 8:21:16 PM


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  • HAL Id : hal-00468947, version 1


Mihai Telescu, Noël Tanguy, Pascale Bréhonnet, Pierre Vilbé, Léon-Claude Calvez. Low Complexity Equivalent Circuit Models for VLSI Interconnects. 10th IEEE Workshop on Signal Propagation on Interconnects, May 2006, Berlin-Mitte, Germany. pp.271-274. ⟨hal-00468947⟩



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