Skip to Main content Skip to Navigation
Conference papers

Low Complexity Equivalent Circuit Models for VLSI Interconnects

Mihai Telescu 1, 2 Noël Tanguy 1, 2 Pascale Bréhonnet 1, 2 Pierre Vilbé 1, 2 Léon-Claude Calvez 1, 2
1 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (UMR 3192)
2 LEST - Laboratoire d'Electronique et Systèmes de Télécommunications
Abstract : In this paper we present a technique for generating low complexity equivalent circuit models for VLSI circuit interconnects via the Laguerre-Gram model order reduction (MOR) method developed by our team. We discuss model passivity and equivalent circuit implementation and then show the advantages of our method in preserving important signal parameters such as rise time, delay and overshoot.
Keywords : othogonal functions model order reduction macro-modeling interconnects signal integrity
Document type :
Conference papers
Complete list of metadatas

Cited literature [5 references]  Display  Hide  Download
https://hal.univ-brest.fr/hal-00468947
Contributor : Noël Tanguy <>
Submitted on : Thursday, April 1, 2010 - 10:58:06 AM
Last modification on : Wednesday, June 24, 2020 - 4:18:37 PM
Long-term archiving on: : Friday, July 2, 2010 - 8:21:16 PM

File

Vignette du document
SPI2006_IEEE_telescu.pdf
Publisher files allowed on an open archive

Identifiers

  • HAL Id : hal-00468947, version 1

Collections

CNRS | UNIV-BREST | LAB-STICC_UBO | LAB-STICC | INSTITUT-TELECOM

Citation

Mihai Telescu, Noël Tanguy, Pascale Bréhonnet, Pierre Vilbé, Léon-Claude Calvez. Low Complexity Equivalent Circuit Models for VLSI Interconnects. 10th IEEE Workshop on Signal Propagation on Interconnects, May 2006, Berlin-Mitte, Germany. pp.271-274. ⟨hal-00468947⟩

Export

BibTeX TEI DC DCterms EndNote

Share

Metrics

Record views

213

Files downloads

319