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Conference papers

Low Complexity Equivalent Circuit Models for VLSI Interconnects

Mihai Telescu 1, 2 Noël Tanguy 1, 2 Pascale Bréhonnet 1, 2 Pierre Vilbé 1, 2 Léon-Claude Calvez 1, 2
1 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (UMR 3192)
2 LEST - Laboratoire d'Electronique et Systèmes de Télécommunications
Abstract : In this paper we present a technique for generating low complexity equivalent circuit models for VLSI circuit interconnects via the Laguerre-Gram model order reduction (MOR) method developed by our team. We discuss model passivity and equivalent circuit implementation and then show the advantages of our method in preserving important signal parameters such as rise time, delay and overshoot.
Keywords : othogonal functions model order reduction macro-modeling interconnects signal integrity
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CNRS | UNIV-BREST | LAB-STICC_UBO | LAB-STICC | INSTITUT-TELECOM

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Mihai Telescu, Noël Tanguy, Pascale Bréhonnet, Pierre Vilbé, Léon-Claude Calvez. Low Complexity Equivalent Circuit Models for VLSI Interconnects. 10th IEEE Workshop on Signal Propagation on Interconnects, May 2006, Berlin-Mitte, Germany. pp.271-274. ⟨hal-00468947⟩

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