Low Complexity Equivalent Circuit Models for VLSI Interconnects
Abstract
In this paper we present a technique for generating low complexity equivalent circuit models for VLSI circuit interconnects via the Laguerre-Gram model order reduction (MOR) method developed by our team. We discuss model passivity and equivalent circuit implementation and then show the advantages of our method in preserving important signal parameters such as rise time, delay and overshoot.
Origin : Publisher files allowed on an open archive
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