Low Complexity Equivalent Circuit Models for VLSI Interconnects - Université de Bretagne Occidentale Access content directly
Conference Papers Year : 2006

Low Complexity Equivalent Circuit Models for VLSI Interconnects

Abstract

In this paper we present a technique for generating low complexity equivalent circuit models for VLSI circuit interconnects via the Laguerre-Gram model order reduction (MOR) method developed by our team. We discuss model passivity and equivalent circuit implementation and then show the advantages of our method in preserving important signal parameters such as rise time, delay and overshoot.
Fichier principal
Vignette du fichier
SPI2006_IEEE_telescu.pdf (1.77 Mo) Télécharger le fichier
Origin : Publisher files allowed on an open archive
Loading...

Dates and versions

hal-00468947 , version 1 (01-04-2010)

Identifiers

  • HAL Id : hal-00468947 , version 1

Cite

Mihai Telescu, Noël Tanguy, Pascale Bréhonnet, Pierre Vilbé, Léon-Claude Calvez. Low Complexity Equivalent Circuit Models for VLSI Interconnects. 10th IEEE Workshop on Signal Propagation on Interconnects, May 2006, Berlin-Mitte, Germany. pp.271-274. ⟨hal-00468947⟩
94 View
244 Download

Share

Gmail Facebook X LinkedIn More