The two primary measurements for performance in storage and memory systems are latency and throughput. It is interesting to see how the memory DIMMs are populated on the server board impact performance. The system bus speed is important when communicating over the Quick Path Interconnect (QPI) to the other CPU local memory resources. This is a crucial part of the performance of systems with a Non-Uniform Memory Access (NUMA). This paper investigates the best practice approaches to optimize performance which have applied to the last few CPU and chipset generations.