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Conference Papers Year : 2016

Robust nonlinear models for CMOS buffers

Abstract

For over a decade, buffer macromodeling has been a topic of great interest for the integrated circuit industry. The performance assessment of high-speed datalinks requires efficient means of simulating IC ports making compact and accurate behavioral models valuable instruments. In the present communication a new modeling technique, with several important advantages is described. The approach is purely “black-box”, relying exclusively on the observation of the external port voltages and currents safeguarding intellectual property. Unlike the standard algorithms currently used in EDA tools, the method described in this paper models the input-output behavior by means of a simple nonlinear system easy to identify and implement. Good model performance in overclocking conditions is an important advantage.

Dates and versions

hal-01342082 , version 1 (05-07-2016)

Identifiers

Cite

Chérif El Valid Diouf, Mihai Telescu, Noël Tanguy, Igor Simone Stievano, F.G. Canavero. Robust nonlinear models for CMOS buffers. 20th IEEE Workshop on Signal and Power Integrity (SPI), May 2016, Turin, Italy. ⟨10.1109/SaPIW.2016.7496284⟩. ⟨hal-01342082⟩
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