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Cache-aware real-time scheduling simulator: implementation and return of experience

Hai-Nam Tran 1 Frank Singhoff 1 Stéphane Rubini 1 Jalil Boukhobza 1
1 Lab-STICC_UBO_CACS_MOCS
UBO - Université de Brest, Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
Abstract : Evaluating cache related preemption delay (CRPD) in preemptive scheduling context of Real-Time Embedded System (RTES) stays an open issue despite of its practical importance. Indeed, various parameters should be taken into account such as memory layout, cache utilization, processor utilization, priority assignment and scheduling algorithm. In state-of-the-art work, dependencies amongst those parameters are not investigated with precision because of the lack of scheduling analysis tool taking them into account. In this article, we present a tool to investigate and evaluate scheduling analysis of RTES with cache memory and various scheduling parameters. The work consists in modeling guidelines and implementation of a cache-aware scheduling simulator. Implementation is made in Cheddar, an open-source scheduling analyzer, which is freely available to researchers and practitioners. Experiments are conducted in order to illustrate applicability and performance of our tool. Furthermore, we discuss about implementation issues, problems raised and lessons learned from those experiments.
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https://hal.univ-brest.fr/hal-01302239
Contributor : Jalil Boukhobza Connect in order to contact the contributor
Submitted on : Wednesday, April 13, 2016 - 6:06:23 PM
Last modification on : Monday, October 11, 2021 - 2:23:12 PM

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Hai-Nam Tran, Frank Singhoff, Stéphane Rubini, Jalil Boukhobza. Cache-aware real-time scheduling simulator: implementation and return of experience. ACM SIGBED Review, Association for Computing Machinery (ACM), 2016, Special Issue on the 5th Embedded Operating Systems Workshop (EWiLi 2015), 13 (1), pp.22-28 ⟨10.1145/2907972.2907975⟩. ⟨hal-01302239⟩

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