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Architecture Models Refinement for Fine Grain Timing Analysis of Embedded Systems

Etienne Borde 1 Smail Rahmoun 1, 2 Fabien Cadoret 1 Laurent Pautet 1 Frank Singhoff 3 Pierre Dissaux 4 
3 Lab-STICC_UBO_CACS_MOCS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance, UBO - Université de Brest
Abstract : As real-time systems have become more and more complex, architects rely on abstract models of computation in order to design and analyse these systems. In order to ease the production of source code that respects such models of computation, developper can take advantage of code generators and/or middleware. However, when analyzing an abstract model of computation, timing overheads due to generated code or middleware components are not taken into account. Answering this issue is even more problematic in the domain of embedded systems because of the variability of execution platforms. To tackle this problem, we present in this paper a model refinement and timing analysis framework: abstract models of computation are first transformed in more precise models, which include the timing characteristics of the execution platform. These refined models are then used for a more precise timing analysis. The experiment results we present in this paper show that our method can deal with realistic software architecture of real-time systems.
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https://hal.univ-brest.fr/hal-01121019
Contributor : Frank Singhoff Connect in order to contact the contributor
Submitted on : Friday, February 27, 2015 - 11:07:06 AM
Last modification on : Tuesday, October 18, 2022 - 8:34:05 AM

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  • HAL Id : hal-01121019, version 1

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Etienne Borde, Smail Rahmoun, Fabien Cadoret, Laurent Pautet, Frank Singhoff, et al.. Architecture Models Refinement for Fine Grain Timing Analysis of Embedded Systems. IEEE International Symposium on Rapid System Prototyping, Oct 2014, New Dehli, India. ⟨hal-01121019⟩

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