Instruction cache in hard real-time systems: modeling and integration in scheduling analysis tools with AADL

Hai-Nam Tran 1 Frank Singhoff 1 Stéphane Rubini 1 Jalil Boukhobza 1
1 Lab-STICC_UBO_CACS_MOCS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance, UBO - Université de Brest
Abstract : Cache prediction for real-time systems in a preemptive scheduling context is still an open issue despite its practical importance. In this paper, we propose a modeling approach for taking into account the cache memory in realtime scheduling analysis. The goal is to have a simple but practical implementation to handle the cache memory with a real-time scheduling analyzer. The proposed contribution consists of three main parts: (1) modeling the targeted system with the Architecture Analysis and Design Language (AADL), (2) applying the cache analysis methods in a real time scheduling analysis tool and (3) performing scheduling simulation to access schedulability. For such a purpose, we present an extension of both the scheduling analysis toolCheddarand of the AADL modeling language in order to integrate the cache modeling and analysis methodology we proposed. Experiments are presented to illustrate our propositions. They provide results on analysis that show examples of the timing impact of task preemption as well as the increase in overall responses time of the task set. This impact is important and the developed tool provides means to precisely assess it.
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Conference papers
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https://hal.univ-brest.fr/hal-01067654
Contributor : Jalil Boukhobza <>
Submitted on : Tuesday, September 23, 2014 - 5:25:01 PM
Last modification on : Monday, February 25, 2019 - 3:14:10 PM

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INSTITUT-TELECOM | UNIV-BREST | LAB-STICC_ENIB | ENIB | LAB-STICC | LAB-STICC_UBO | IBNM

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Hai-Nam Tran, Frank Singhoff, Stéphane Rubini, Jalil Boukhobza. Instruction cache in hard real-time systems: modeling and integration in scheduling analysis tools with AADL. International Conference on Embedded and Ubiquitous Computing (EUC), Aug 2014, Milan, Italy. pp.104-111, ⟨10.1109/EUC.2014.24⟩. ⟨hal-01067654⟩

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