New techniques for selecting test frequencies for linear analog circuits

Mohand Bentobache 1, 2, * Ahcène Bounceur 3 Reinhardt Euler 3 Yann Kieffer 4 Salvador Mir 5
* Auteur correspondant
1 LAMOS - Laboratoire de Modélisation et Optimisation des Systèmes [Béjaïa]
2 Université Amar Telidji - Laghouat (ALGERIA)
3 Lab-STICC_UBO_CACS_MOCS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance, UBO - Université de Brest
4 G-SCOP_ROSP - ROSP
G-SCOP - Laboratoire des sciences pour la conception, l'optimisation et la production
5 RMS
TIMA - Techniques of Informatics and Microelectronics for integrated systems Architecture
Abstract : In this paper we show that the problem of minimizing the number of test frequencies necessary to detect all possible faults in a multi-frequency test approach for linear analog circuits can be modeled as a set covering problem. We will show in particular, that under some conditions on the considered faults, the coefficient matrix of the problem has the strong consecutive-ones property and hence the corresponding set covering problem can be solved in polynomial time. For an efficient solution of the problem, an interval graph formulation is also used and a polynomial algorithm using the interval graph structure is suggested. The optimization of test frequencies for a case-study biquadratic filter is presented for illustration purposes. Numerical simulations with a set of randomly generated problem instances demonstrate two different implementation approaches to solve the optimization problem very fast, with a good time complexity.
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Communication dans un congrès
International Conference on Very Large Scale Integration (VLSI-SoC), Oct 2013, Istamboul, Turkey. 2013
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Soumis le : jeudi 29 août 2013 - 06:53:22
Dernière modification le : mercredi 16 mai 2018 - 18:30:05
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Mohand Bentobache, Ahcène Bounceur, Reinhardt Euler, Yann Kieffer, Salvador Mir. New techniques for selecting test frequencies for linear analog circuits. International Conference on Very Large Scale Integration (VLSI-SoC), Oct 2013, Istamboul, Turkey. 2013. 〈hal-00855154〉

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