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Conference Papers Year : 2013

Statistical modelling of analog circuits for test metrics computation

Abstract

Analog Built-In Test (BIT) techniques should be evaluated at the design stage, before the real production, by estimating the analog test metrics, namely Test Escapes (TE) and Yield Loss (YL). Due to the lack of comprehensive fault models, these test metrics are estimated under process variations. In this paper, we estimate the joint cumulative distribution function (CDF) of the output parameters of a Circuit Under Test (CUT) from an initial small sample of devices obtained from Monte Carlo circuit simulation. We next compute the test metrics in ppm (parts-per-million) directly from this model, without sampling the density as in previous works. The test metrics are obtained very fast since the computation does not depend on the size of the output parameter space and there is no need for density sampling. An RF LNA modeled with a Gaussian copula is used to compare the results with past approaches.
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Dates and versions

hal-00765157 , version 1 (14-12-2012)

Identifiers

  • HAL Id : hal-00765157 , version 1

Cite

Kamel Beznia, Ahcène Bounceur, Salvador Mir, Reinhardt Euler. Statistical modelling of analog circuits for test metrics computation. IEEE International Conference on Design & Technology of Integrated Systems in nanoscale era (DTIS'13), Mar 2013, Abu Dhabi, United Arab Emirates. ⟨hal-00765157⟩
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