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Conference Papers Year : 2011

Regular 2D Nasic-based Architecture and Design Space Exploration

Abstract

As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of dif- ferent fabrics and architectures are currently under investigation. Unfortunately, at this time, no unified modeling exists to offer sound support for algorithmic design space exploration, with no compromise on device feasibility. This work presents a NASIC-compliant application-specific computing architecture template along with its performance models and optimization policies that support domain-space ex- ploration. This architecture has up to 29X density advantage over CMOS, is completely compatible with the NASIC manufacturing pathway, and enables the creation of unique max-rate pipelined systems.
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Dates and versions

hal-00598850 , version 1 (07-06-2011)

Identifiers

  • HAL Id : hal-00598850 , version 1

Cite

Ciprian Teodorov, Pritish Narayanan, Loic Lagadec, Catherine Dezan. Regular 2D Nasic-based Architecture and Design Space Exploration. NANOARCH 2011, Jun 2011, San Diego, United States. pp.70-77. ⟨hal-00598850⟩
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