As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of dif- ferent fabrics and architectures are currently under investigation. Unfortunately, at this time, no unified modeling exists to offer sound support for algorithmic design space exploration, with no compromise on device feasibility. This work presents a NASIC-compliant application-specific computing architecture template along with its performance models and optimization policies. From the tool-flow perspective, this architecture is similar to antifuse configurable architectures hence we propose a FPGA SDK based programming environment that support domain-space exploration.