A 0.18 mu m CMOS implementation of on-chip analogue test signal generation from digital test patterns - Université de Bretagne Occidentale Access content directly
Conference Papers Year : 2004

A 0.18 mu m CMOS implementation of on-chip analogue test signal generation from digital test patterns

Abstract

The test of analogue and mixed-signal (AMS) cores requires the use of expensive AMS testers and accessibility to internal analogue nodes. The test cost can be considerably reduced by the use of built-in-self-test (BIST) techniques. One of these techniques consists of generating analogue test signals from digital test patterns (obtained via Sigma Delta modulation) and converting the responses of the analogue modules into digital signatures that are compared with the expected ones. This paper presents an implementation of the analogue test signal generation part that includes programmability of the circuit blocks, leading to an improvement of performance and a reduction of circuit size with respect to previous approaches. A 0.18 mu m CMOS circuit has been designed and fabricated, allowing the generation of test signals ranging from 10 Hz to 1 MHz.
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Dates and versions

hal-00522108 , version 1 (29-09-2010)

Identifiers

  • HAL Id : hal-00522108 , version 1

Cite

L. Rolindez, Salvador Mir, Guillaune Prenat, Ahcène Bounceur. A 0.18 mu m CMOS implementation of on-chip analogue test signal generation from digital test patterns. Design,-Automation-and-Test-in-Europe, May 2004, France. pp.0. ⟨hal-00522108⟩
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