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Functional test compaction by statistical modelling of analogue circuits

Abstract : In this paper, we address the problem of functional test compaction of analogue circuits by using a statistical model of the performances of the Circuit Under Test (CUT). The statistical model is obtained using data from a Monte-Carlo simulation and uses a multi-normal law to estimate the joint Probability Density Function (PDF) of the circuit performances at the design stage. The functional test compaction method is based on the minimization of the defect level, again at the design stage, that is calculated from the estimated PDF and the actual specifications of the circuit performances. The suitability of the actual reduced functional test set for production test must next be evaluated in terms of its capability of detecting catastrophic and parametric faults.
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https://hal.univ-brest.fr/hal-00522016
Contributor : Ahcène Bounceur <>
Submitted on : Wednesday, September 29, 2010 - 1:04:27 PM
Last modification on : Monday, September 21, 2020 - 12:24:05 PM

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  • HAL Id : hal-00522016, version 1

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N. Akkouche, Ahcène Bounceur, Salvador Mir, Emmanuel Simeu. Functional test compaction by statistical modelling of analogue circuits. 13th IEEE International Mixed-Signals Testing Workhop (IMSTW'07), May 2008, France. pp.0. ⟨hal-00522016⟩

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