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Test limit evaluation for an ADC Design-for-Test approach by using a CAT platform

Abstract : This paper presents a Design-for-Test method for folded and interpolated analog-to-digital converters. The test approach samples relative voltage deviations among internal circuit nodes. A fault simulation is used to establish the fault detection threshold of the BIST by using a CAT platform.
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https://hal.univ-brest.fr/hal-00521991
Contributor : Ahcène Bounceur <>
Submitted on : Wednesday, September 29, 2010 - 11:48:24 AM
Last modification on : Wednesday, July 22, 2020 - 3:01:09 AM

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  • HAL Id : hal-00521991, version 1

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Y. Lechuga, Ahcène Bounceur, R. Mozuelos, Mar Matinez, S. Bracho, et al.. Test limit evaluation for an ADC Design-for-Test approach by using a CAT platform. 23rd International Conference on Design of Circuits and Integrated Systems (DCIS'08),, Nov 2008, France. pp.0. ⟨hal-00521991⟩

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