Reconfigurable hardware: The holy grail of matching performance with programming productivity

Abstract : Many reconfigurable hardware architectures have been proposed so far, ranging from FPGAs to coarse grained architectures. Reconfigurability can be intended in several ways, and a number of diverse solutions have been proposed. One of the most relevant issues that have emerged is that the performance gain offered by reconfigurable hardware is balanced by relevant difficulties in their programming, which often inhibit its utilization in many appealing fields and ultimately jeopardize its diffusion. The solution for enabling higher productivity in application mapping likely do not reside only in the development of better tools, but also of more usable designs. This paper gives an overview of different reconfigurable architectures and related design flows proposed over the last years, including commercial offers and efforts coming from academia, analyzes the challenges they pose to the application developer and focuses on the latest alternatives to mitigate the design productivity issue.
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Communication dans un congrès
IEEE Press. International Conference on Field Programmable Logic and Applications, Sep 2008, Heidelberg, Germany. pp.409 - 414, 2008, 〈10.1109/FPL.2008.4629972〉
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http://hal.univ-brest.fr/hal-00518344
Contributeur : Picard Damien <>
Soumis le : vendredi 17 septembre 2010 - 08:54:10
Dernière modification le : mardi 16 janvier 2018 - 15:54:14

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Claudio Brunelli, Fabio Garzia, Jari Nurmi, Fabio Campi, Damien Picard. Reconfigurable hardware: The holy grail of matching performance with programming productivity. IEEE Press. International Conference on Field Programmable Logic and Applications, Sep 2008, Heidelberg, Germany. pp.409 - 414, 2008, 〈10.1109/FPL.2008.4629972〉. 〈hal-00518344〉

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