L. David, C. Cregut, F. Huret, Y. Quéré, and F. Et-nyer, Return Path Assumption Validation for Inductance Modeling in Digital Design, Proc. of Signal Propagation on Interconnects (SPI), pp.93-96, 2005.
DOI : 10.1109/TADVP.2007.896002
URL : https://hal.archives-ouvertes.fr/hal-00176177

S. Yu, Loop-based inductance extraction and modeling for multiconductor on-chip interconnects, IEEE Transactions on Electron Devices, vol.53, issue.1, pp.135-145, 2006.
DOI : 10.1109/TED.2005.860655

B. Krauter and S. Et-mehrtra, Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis, Proceedings of the 35th annual conference on Design automation conference , DAC '98, pp.303-308, 1998.
DOI : 10.1145/277044.277133