Fine Grain Parallel Decoding of Turbo Product Codes: Algorithm and Architecture

Abstract : In turbo decoding of product codes, we propose an algorithm implementation, based on Chase-Pyndiah algorithm, which exhibits a modular, simple structure with fine grain parallelism. It is implemented into deep pipelined architectures, including an interleaving block decoding scheme, with good potential on FPGAs and MP-SoCs targets. We include an evaluation of the essential parameters of those architectures, which are situated in a different area of the block turbo decoder implementation design space.
Type de document :
Communication dans un congrès
5th international symposium on turbo codes and related topics, Sep 2008, Lausanne, Switzerland. pp.90-95, 2008
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http://hal.univ-brest.fr/hal-00487334
Contributeur : Catherine Dezan <>
Soumis le : vendredi 28 mai 2010 - 16:19:40
Dernière modification le : mercredi 11 juillet 2018 - 07:49:55

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  • HAL Id : hal-00487334, version 1

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Thierry Goubier, Catherine Dezan, Bernard Pottier, Christophe Jégo. Fine Grain Parallel Decoding of Turbo Product Codes: Algorithm and Architecture. 5th international symposium on turbo codes and related topics, Sep 2008, Lausanne, Switzerland. pp.90-95, 2008. 〈hal-00487334〉

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