Equalization of Interconnect Propagation Delay with Negative Group Delay Active Circuits

Blaise Ravelo; André Pérennec; Marc Le Roy

Equalization of Interconnect Propagation Delay with Negative Group Delay Active Circuits

Blaise Ravelo ¹ André Pérennec ¹ Marc Le Roy ^{1, *}

* Auteur correspondant

1 Lab-STICC_UBO_MOM_DIM

UBO - Université de Brest, Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance

Abstract : In this paper, we propose a technique to compensate the propagation delay and losses in VLSI interconnects by using negative group delay (NGD) active circuits. This study uses the RLC models of interconnect lines currently considered in VLSI circuits. The circuit proposed here is based on a cell consisting of a Field Effect Transistor (FET) in parallel with a series RL passive network. We also describe the synthesis method to achieve simultaneousely a significant negative group delay and gain. Simulations allow us to first verify the performance of the NGD circuit and also show a restoration of the distorted signal shape as well as a reduction of propagation delay

Type de document :

Communication dans un congrès

11th IEEE Workshop on Signal Propagation on Interconnects (SPI'07), May 2007, Genova, Italy. pp.15-18, 2007

Domaine :

Sciences de l'ingénieur [physics] / Electronique

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http://hal.univ-brest.fr/hal-00468111
Contributeur : Marc Le Roy <>
Soumis le : mardi 30 mars 2010 - 09:46:41
Dernière modification le : mardi 16 janvier 2018 - 15:54:25
Document(s) archivé(s) le : jeudi 1 juillet 2010 - 20:14:50

spi07_blaise_ravelo.pdf

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