Equalization of Interconnect Propagation Delay with Negative Group Delay Active Circuits - Université de Bretagne Occidentale Access content directly
Conference Papers Year : 2007

Equalization of Interconnect Propagation Delay with Negative Group Delay Active Circuits

Blaise Elysée Guy Ravelo
  • Function : Author
  • PersonId : 867782
André Pérennec
Marc Le Roy
Connectez-vous pour contacter l'auteur

Abstract

In this paper, we propose a technique to compensate the propagation delay and losses in VLSI interconnects by using negative group delay (NGD) active circuits. This study uses the RLC models of interconnect lines currently considered in VLSI circuits. The circuit proposed here is based on a cell consisting of a Field Effect Transistor (FET) in parallel with a series RL passive network. We also describe the synthesis method to achieve simultaneousely a significant negative group delay and gain. Simulations allow us to first verify the performance of the NGD circuit and also show a restoration of the distorted signal shape as well as a reduction of propagation delay

Domains

Electronics
Fichier principal
Vignette du fichier
spi07_blaise_ravelo.pdf (199.51 Ko) Télécharger le fichier
Origin Files produced by the author(s)
Loading...

Dates and versions

hal-00468111 , version 1 (30-03-2010)

Identifiers

  • HAL Id : hal-00468111 , version 1

Cite

Blaise Elysée Guy Ravelo, André Pérennec, Marc Le Roy. Equalization of Interconnect Propagation Delay with Negative Group Delay Active Circuits. 11th IEEE Workshop on Signal Propagation on Interconnects (SPI'07), May 2007, Genova, Italy. pp.15-18. ⟨hal-00468111⟩
107 View
802 Download

Share

Gmail Mastodon Facebook X LinkedIn More