Fault attacks aim to disturb integrated circuits using physical methods to break a security system or steal information. Nowadays, a particular attention has been paid to fault attacks on SoCs (System-on-Chip). A SoC is made up of numerous IPs which are connected to each other by a communication architecture. This work focuses on a RISC-V based SoC with a wishbone bus. It aims to study the security of the bus against fault attacks. Using a simulation environment, an automate-attack script, generated by Python, targets all the registers within the bus to identify all the vulnerabilities in the communication architecture. After integrating some countermeasures, the resistance to several fault models of the extended communication structure is measured and discussed.