Flashing the Memory Hierarchy: an Overview on Flash Memory Internals

Jalil Boukhobza 1 Stéphane Rubini 1
1 Lab-STICC_UBO_CACS_MOCS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance, UBO - Université de Brest
Abstract : NAND Flash memories have gained a solid foothold in the embedded systems domain due to its attractive characteristics in terms of size, weight, shock resistance, power consumption, and data throughput. Moreover, flash memories tend to be less confined to the embedded domain, as it can be observed through the market explosion of flash-based storage systems (average growth of the NVRAM is reported to be about 69% up to 2015, partly due to flash memory demand). In this presentation, we shed some light on NAND flash memory NVRAM. After a global presentation of its architecture and very specific constraints, we describe throughout some examples the different ways to manage flash memories in embedded systems which are 1) the use of a hardware Flash Translation layer (FTL), or 2) a dedicated Flash File System (FFS) software support implemented within the operating system kernel. Some performance and energy consumption issues will also be addressed as flash memory presents an asymmetric performance model for read/write operations. Some of our contributions on flash memory architecture design (cache and FTL design) will be discussed and the talk will end up on a discussion about the integration of flash memories (in storage or/and in memory systems).
Keywords : Flash memory
Type de document :
Communication dans un congrès
Journée Logiciels Embarqués et Architectures Matérielles du GDR SoC-SiP, Nov 2012, Paris, France
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http://hal.univ-brest.fr/hal-00758454
Contributeur : Jalil Boukhobza <>
Soumis le : jeudi 29 novembre 2012 - 13:25:48
Dernière modification le : mardi 16 janvier 2018 - 15:54:23

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  • HAL Id : hal-00758454, version 1

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Jalil Boukhobza, Stéphane Rubini. Flashing the Memory Hierarchy: an Overview on Flash Memory Internals. Journée Logiciels Embarqués et Architectures Matérielles du GDR SoC-SiP, Nov 2012, Paris, France. 〈hal-00758454〉

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