Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder

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Communication dans un congrès
J. Becker et al. ARC 2009, the 5th International Workshop on Applied Reconfigurable Computing, Mar 2009, Germany. Springer Berlin / Heidelberg, 5453, pp.287-292, 2009, Lecture Notes in Computer Science. 〈10.1007/978-3-642-00641-8_30〉
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http://hal.univ-brest.fr/hal-00490480
Contributeur : Erwan Fabiani <>
Soumis le : mardi 8 juin 2010 - 17:17:54
Dernière modification le : mardi 16 janvier 2018 - 15:54:23

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Samar Yazdani, Thierry Goubier, Bernard Pottier, Catherine Dezan. Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder. J. Becker et al. ARC 2009, the 5th International Workshop on Applied Reconfigurable Computing, Mar 2009, Germany. Springer Berlin / Heidelberg, 5453, pp.287-292, 2009, Lecture Notes in Computer Science. 〈10.1007/978-3-642-00641-8_30〉. 〈hal-00490480〉

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